Multilayer module with thinfilm redistribution area

ABSTRACT

The invention relates to a multilayer module 20 for packaging of at least one electronic component, such as the integrated circuit chips 21, 22. The module 20 comprises a thickfilm structure and a thinfilm structure. The thinfilm structure provides an interface between the electronic components and the thickfilm structure. The thinfilm structure comprises a first powerplane and a redistribution wiring structure. The topmost layer of conductors of the thickfilm structure is a second powerplane so that an electrical structure approaching a triplate structure is realized.

The present invention relates to an improved multilayer module forpackaging of at least one electronic component and to a method forfabricating such a multilayer module.

As VLSI circuits become more dense, there is a need in the art to havesemiconductor packaging structures that can take full advantage of thedensity and speed of state of the art VLSI devices. Present day modulesmade of ceramic, typically multilayered ceramic modules are normallymounted onto cards or boards, with cards or boards combined together toform the central processing unit (CPU) of a computer. The multilayeredceramic (MLC) modules typically have VLSI chips mounted on thetopsurface and typically have pins on the bottomsurface thereof eventhough there are multilayer ceramic modules which have alternativemounting means such as solderbumps.

As integrated circuit speeds and packaging densities-increase theimportance of the packaging technology becomes increasingly significant.For example, as devices approach gigahertz speed, inductance effects andthe like in the packaging become significant. Such inductance effectsmay arise from, for example, switching and the like, and areparticularly problematic in power and ground leads. Inductance effectsin the package can cause ground bounce, signal cross-talk, and the like.

The multilayer ceramic (MLC) multichip module (MCM) technologyintroduced by IBM represents a revolutionary advance in packaging stateof the art and provides the high-performance wiring needed to exploitthe gains achieved with todays integrated circuits logic devices. Thistechnology is described for example in A. J. Blodgett, "A MultilayerCeramic Multi-Chip Module," Proceedings of the Electronic ComponentsConference, IEEE, New York, 1988, pp. 283-285 and B. T. Clark and Y. M.Hill, "IBM Multichip Multilayer Ceramic Modules for LSI Chips--DesignsFor Performance and Density," IEEE Transactions Components, Hybrids.Manuf. Technology, CHMT-3, 89-93 (1980). Furthermore, the articles by A.J. Blodgett, D. R. Barbour, "Thermal Conduction Module: AHigh-Performance Multilayer Ceramic Package", IBM J. Res. Develop., vol.26, no. 1, January 1982, and by A. J. Blodgett, "MicroelectronicPackaging", Scientific American, July 1983, vol. 249, no. 1 describethis technology.

Even though the above referenced IBM technology mainly relies onthickfilm technology for the production of multilayer modules, proposalshave been made in the prior art to combine thickfilm and thinfilmtechnology for the packaging of integrated circuits chips. U.S. Pat. No.4 958 258 describes a modular hybrid microelectronic structure with ahigh density of integration. The structure comprises, on one face, anencapsulated hybrid circuit that groups together circuits with a highdensity of integration, formed by one or more semiconductor chips, saidcircuits being mounted on a thin-layer substrate. The thin-layersubstrate is grown on a face of supporting, thick-layer substrate,preferably made of co-baked ceramic. Encapsulate, microelectroniccomponents such as monolithic, integrated circuits are borne on theother face of the substrate. The interconnections among variouscomponents and with the exterior are made within and through the layersof the supporting substrate so that no wire or connection appears on theuncovered parts of the substrate.

Furthermore U.S. Pat. No. 4 549 200 and U.S. Pat. No. 4 916 259 proposethe combination of thickfilm and thinfilm technologies for theproduction of packaging modules.

The fast development of the VLSI/ULSI CMOS chip technology aims tofurther increase the circuit density. This goes hand in hand with acorresponding increase in the number of I/O counts of a chip which ismade possible by the FLIP CHIP technology, especially by theC4-technology. Todays multilayer module technologies are mainly based oneither multilayer ceramic or multilayer glass-ceramic thickfilmtechnology. In both cases the line width, line spacing and insulatorthickness are limited by the accompanying thickfilm technologies. Thesame restrictions are valid for card and board technologies which makeuse of multilayer glass epoxy and multilayer teflon based insulatormaterials. Therefore the thickfilm chip carrier technologies do notalways satisfy the requirements of modern highly integrated chiptechnologies.

It is therefore an object of the present invention to provide animproved multilayer module combining thickfilm and thinfilmtechnologies.

The underlying problem of the invention is solved by a multilayer moduleaccording to claim 1.

According to the invention multilayer thickfilm and multilayer thinfilmtechnologies are combined. The multilayer thinfilm structure on top ofthe multilayer thickfilm structure significantly reduces the number oflayers of thickfilm needed for the construction of a module. This is dueto the line width below 25 micrometer which is made possible by thethinfilm technology as compared to line width limited to 80-100micrometer of thickfilm multilayer technologies.

It is particularly advantageous to realize the redistribution area inthe uppermost portion of the multilayer module in thinfilm technology,because the redistribution area is particularly sensitive to noise dueto the high I/O count of modern chips and the narrow pitch of the chipfootprint. The thinfilm structure provides an interface between theelectronic component to be packaged and the underlying thickfilmstructure. The redistribution wiring of the thinfilm structure isinterposed between a first powerplane such as ground and a secondpowerplane such as a voltage plane. The second powerplane is the firstpowerplane of the thickfilm structure. Even though the distance of thethinfilm redistribution wiring structure from the second powerplane ofthe thickfilm structure is much greater than the distance from thethinfilm redistribution wiring structure to the first powerplane of thethinfilm structure which is situated in the uppermost region of thethinfilm structure, the electrical characteristics of the thinfilmredistribution wiring structure is comparable to an ideal triplatestructure which is normally used in the X/Y wiring area of a multilayerceramics module.

Thereby the provision of a second powerplane forming part of thethinfilm structure is made unnecessary. The production of such athinfilm structure having only two metal layers is much easier and lesscostly than the production of a thinfilm structure having an idealtriplate structure like in the X/Y wiring area of the module whichconsists of four metal layers (GND-X-Y-Voltage).

According to the invention an equivalent structure can also be used fora multilayer printed circuit board. In this case the thickfilm structureforms the underlying mechanical structure of the multilayer printedcircuit board. If such a multilayer module or multilayer printed circuitboard is incorporated into a computer system, this is beneficial for theoverall performance of the system and also reduces the production costsof the computer system. The increase of the performance of the computersystem is due to the fact that the improved multilayer module and/ormultilayer printed circuit boards according to the invention allow thesystem to take full advantage of high performance integrated circuitchips.

One way of carrying out the invention is described in detail below withreference to the drawings which illustrate only one specific embodiment,in which:

FIG. 1 a schematic, cross sectional view of a state of the artmultilayer module in thickfilm technology;

FIG. 2 is a schematic, cross sectional view of a multilayer moduleaccording to the invention;

FIG. 3 is a magnified cross sectional view of the upper portion of amultilayer module according to the invention; and

FIG. 4 is a circuit diagram of a portion of the redistribution wiringstructure in the thinfilm structure.

FIG. 1 shows a state of the art module 3. The module carries chips 1 and2 which are connected to the module by the C4-balls 4 and 5. TheC4-balls 4 connect the signal I/Os of the chips 1 and 2 to the modulewhereas the solid C4-balls 5 connect the voltage and ground terminals ofthe chips 1 and 2 to the module 3. In the redistribution area of themodule 3 the signals of the chips 1 and 2 are fanned out. This isnecessary because of the narrow pitch of the chip footprints. Theredistribution area has the redistribution planes R1, R2, R3, R4, R5, .. . , R14. Each redistribution plane is interposed between power andground GND mesh planes 6. The redistribution planes contain horizontalsignal wiring 9 to fan out the signals. The vertical connections in themodule 3 are established by vertical vias 7 and 8. The vertical vias 7carry the signals and the vertical vias 8 carry power and ground. At theend of the redistribution area logic service terminals LST provide theinterface to the X/Y wiring area. The X/Y wiring area comprises X/Ywiring planes which establish the connections from one chip to anotherchip or from one chip to the pins 11 of the module 3. In FIG. 1 only twowiring plane pairs are shown, i.e. X3/Y3 and X4/Y4.

The dense wiring and wire structures in the redistribution area belowthe chip lead to significant off-chip driver noise values due toelectromagnetic coupling and delta I noise voltages. As compared tothis, the electrical characteristics of the X/Y wiring area is muchbetter due to the less dense wiring and the constantly used triplatestructures. In the X/Y wiring area it is guaranteed that the signalwiring is always embedded between voltage and ground mesh planes 6.

The fan-out capability with respect to low noise of the thickfilmtechnology in the redistribution area is limited to I/O counts around500 to 700 signals.

FIG. 2 shows a multilayer module 20 which is designed according to theinvention. The multilayer module 20 has a X/Y wiring area whichcorresponds to the X/Y wiring area of the multilayer module 3 shown inFIG. 1. The X/Y wiring area of the multilayer module 20 is implementedin thickfilm technology like the X/Y wiring area of the module 3,however, instead of a thickfilm redistribution area the module 20 has athinfilm redistribution area.

The thinfilm redistribution area carries the chips 21 and 22, and servesto fan out the signals from chips 21 and 22. The thinfilm technologymakes it possible to realize the redistribution of the signal vias inthe thinfilm redistribution area in one layer of thinfilm wiring. Thethinfilm redistribution area provides an interface between the chips 21and 22 and the thickfilm X/Y wiring area of the module 20. The verticalsignal vias of the thinfilm redistribution area are connected to thethickfilm X/Y wiring area at the logic service terminals.

The topmost layer of wiring of the thinfilm structure is a powerplane,such as a thinfilm ground mesh plane. The design of the topmost area ofthe module 20 is explained in more detail with respect to FIG. 3 whichshows a magnified view of the topmost portion of the multilayer module20 of FIG. 2.

FIG. 3 shows the topmost voltage mesh plane 30 of the X/Y wiring area ofthe module 20. The voltage mesh plane 30 is realized in conventionalthickfilm technology, such as multilayer ceramics. The thickness of thewiring structure of the voltage mesh plane 30 is about 35 micrometers.The voltage mesh plane 30 is contacted by a via 31 which still is in thethickfilm X/Y wiring area. The via 31 penetrates the topmost layer ofthickfilm ceramic of the thickfilm structure of the module 20. Thediameter of the via 31 is about 100 micrometers and the thickness t ofthe topmost thickfilm layer of the X/Y wiring area is about 250micrometers to 350 micrometers. The topmost thickfilm layer of thethickfilm structure is planarized, so that the thickfilm structure has aplanarized ceramic surface at the interface to the overlaying thinfilmstructure.

The thinfilm structure serves as a redistribution area. The thinfilmredistribution area has one layer of thinfilm wiring 33 comprising theportions 33a, 33b, 33c and 33d. The line width of the thinfilm wiring 33is about 25 micrometers as is the line spacing.

The thinfilm structure has a second wiring layer which is a thinfilmground mesh plane 38. The ground mesh plane 38 has holes to implementpads 37 for the connection of electronic components such as integratedcircuit chips 21, 22 to the module 20. In the example considered herethe pads 37 serve as a contact terminal for the C4-balls of the chips21, 22. The thinfilm wiring 33 is separated from the planarized ceramicsurface of the thickfilm X/Y wiring area by a thinfilm layer 34. Thethinfilm wiring 33 is separated from the thinfilm ground mesh plane 38by a second thinfilm layer 35. The thinfilm layer 34 has vias 32 whichconnect the thinfilm wiring 33 to the vias 31 of the thickfilm X/Ywiring area. By way of example only one such via 31 and 32 is shown inFIG. 3. The vias 32 have a diameter of only about 10 micrometers. Theconnection of the via 32 to the via 31 provides a logic service terminal40.

The second thinfilm layer 35 has vias 36 which serve to connect thethinfilm wiring 33 to the pads 37. In FIG. 3 only one such via 36 isshown by way of example. The via 36 connects the portion 33a of thethinfilm wiring 33 to the pad 37. The module 20 has a further thinfilmlayer 41 atop the thinfilm ground mesh plane 38 in order to mechanicallyprotect the underlying structures. The pads 37 are not covered by thethinfilm layer 41. The thickness of the layers 34 and 35 is about 9micrometers, whereas the thickness of the layers 38 and 41 is about 5micrometers.

Even though the distance of the thinfilm redistribution wiring 33 to themultilayer ceramics voltage mesh plane 30 is much greater than thedistance of the redistribution-wiring 33 to the thinfilm ground meshplane 38 the electrical characteristics of this structure approach thecharacteristics of a perfect triplate structure which is realized in theX/Y wiring area for example for the wiring planes X3/Y3 and X4/Y4 inFIG. 2.

The larger distance of the thinfilm wiring 33 to the multilayer ceramicsvoltage mesh plane 30 is compensated by the very short distance of thethinfilm wiring 33 to the thinfilm ground mesh plane 38.

The excellent electrical characteristic of the thinfilm redistributionarea according to the invention is described and compared to othertechnologies in the following table.

    ______________________________________                              Thinfilm Thinfilm                              redistrib.                                       redsitrib.             MLC-   MLC-      "without "with             Redistrib.                    X/Y layers                              triplate"                                       triplate"    ______________________________________    Impedance   45 Ohm   50 Ohm    70 Ohm                                          45 Ohm    propagation               120 ps/cm                        120 ps/cm  70 ps/cm                                          70 ps/cm    delay (ps/cm)    Noise voltage               200 mV   150 mV    300 mV <80 mV    at near end    (5 mm - Vne/mV)    Noise voltage               400 mV   100 mV    150 mV <10 mV    at far end    (Vfe/mV)    ______________________________________

The electrical values indicated in the first column of the table arerepresentative for the multilayer ceramics redistribution area of thestate of the art multilayer module 3 of FIG. 1. The electrical valuesindicated in column 2 of the table are representative for the thickfilmX/Y wiring area of both module 3 of FIG. 1 and module 20 of FIG. 2 and3. Column 3 of the table is representative of a thinfilm redistributionarea without a "triplate" structure. This means that the thinfilm groundmesh plane 38 is left away so that the thinfilm wiring 33 is notinterposed between two power planes. The fourth column of the table isrepresentative of a thinfilm redistribution area as shown in FIG. 3. Itappears from the table that the thinfilm redistribution area accordingto the invention has excellent electrical characteristics as compared tothe other technologies.

FIG. 4 shows a partial topview of the thinfilm wiring 33. The portions33a and 33c of one wire of the thinfilm wiring 33 of FIG. 4 correspondsto the portions 33a and 33c of FIG. 3. This wire of the thinfilm wiringplane 33 is connected by the vias 36 and 32 at its ends.

The wires of the thinfilm wiring plane 33 are arranged in starlikefashion having the point Z as center or--in other words vanishing point.This makes it possible to realize the redistribution in just one plane.

The multilayer module 20 of FIGS. 2, 3 and 4 is fabricated as follows:

First the thickfilm X/Y wiring area of the module 20 is produced using aknown thickfilm technology. Then a layer of thinfilm material, such aspolyimide is deposited atop the thickfilm X/Y wiring area. Thereby thelayer 34 is realized. Subsequently vias 32 are implemented in the layer34.. This can be accomplished by selectively exposing the layer 34 to alaser and subsequently sputtering copper into the vias 32.

In the next step the thinfilm redistribution wiring plane 33 isdeposited atop the layer 34. A second layer of polyimide is deposited atop the redistribution wiring 33. Thereby the layer 35 is realized.Again, the layer 35 is exposed to a laser and the corresponding vias 36are sputtered with copper. Finally the first powerplane is depositedatop the layer 35. Thereby the thinfilm ground mesh plane 38 isrealized.

We claim:
 1. A multilayer module for the packaging of at least oneelectronic component, said module comprising:a thickfilm structurehaving layers of conductors and a thinfilm structure, said thinfilmstructure providing an interface between said electronic component andsaid thickfilm structure, wherein said thinfilm structure comprises afirst power plane (38) and a redistribution wiring structure (33, 33a,33b, 33c, 33d) and wherein the topmost layer of the conductors of saidthickfilm structure is a second power plane (30), the redistributionwiring structure being interposed between said first power plane andsaid second power plane.
 2. A multilayer module according to claim 1wherein the distance between said redistribution wiring structure andsaid second power plane is substantially greater than the distancebetween said redistribution wiring structure and said first power plane.3. A multilayer module according to claim 1 wherein said thickfilm isfabricated from material from the group consisting of: ceramic,glass-ceramic, glass-epoxy, teflon and a flexible foil.
 4. A computersystem incorporating a multilayer module for packaging of at least oneelectronic component, such as a single or multichip module, according toclaim
 1. 5. A method for fabricating a multilayer module according toclaim 1 comprising the steps of:a) fabricating said thickfilm structure;b) depositing a first layer of thinfilm, such as polyimide atop saidthickfilm structure; c) providing vias in said first layer of thinfilm;d) depositing said redistribution wiring structure atop said first layerof thinfilm; e) depositing a second layer of thinfilm, such aspolyimide, atop said redistribution wiring structure; f) providing viasin said second layer of thinfilm; g) depositing said first power planeatop said second layer of thinfilm; and h) providing contact means, suchas contact pads, in said first power plane for connecting saidelectronic component to said module.
 6. A method according to claim 5further comprising a step of depositing a third layer of polyimide atopsaid first power plane except for portions of said first power planewhere said contact means, such as contact pads (37), are provided.
 7. Amethod according to claim 5 further comprising a step of planarizingsaid thickfilm structure prior to carrying out said step b).